This application relies for priority upon Korean Patent Application No. 2001-46775, filed on Aug. 2, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to an EEPROM memory cell structure and a method of forming the same. More specifically, the invention is directed to an EEPROM memory cell structure and a method of forming the same, which can not only maintain operation characteristics, but also reduce area of an EEPROM cell.
An EEPROM memory is a nonvolatile memory that is semi-permanently capable of retaining data in a memory cell even while power is not applied. In particular, the EEPROM memory is an electrically programmable and erasable memory device.
FIG. 1 is a top plan view showing a typical EEPROM memory cell, and FIGS. 2 and 3 are cross-sectional views taken along lines Ixe2x80x94I and IIxe2x80x94II of FIG. 1, respectively.
Referring to FIGS. 1 to 3, the EEPROM memory cell consists of two transistors that are connected in series along an active region 11 formed long in one direction. One of the transistors is a sensing transistor having a floating gate 19, and the other is a selection transistor having a single gate. A bit line contact 25 is connected to a drain region 35 of the selection transistor. A source region 21 of the selection transistor corresponds to a drain region of the sensing transistor. The drain region 21 of the sensing transistor is widened to the substrate under the floating gate 19 constituting the sensing transistor. The sensing transistor includes a tunnel insulation layer 23 surrounded by gate insulation layer 31. The tunnel insulation layer 23 is interposed between the floating gate 19 and the drain region 21. A source region 37 of the sensing transistor is widened to be connected to a common source line 39. In the EEPROM memory cell array, the memory cells are arranged in a matrix of rows and columns. Gate electrodes of the selection transistors in a row are connected with each other to form a word line 13 across the active regions, whereas gate electrodes of the sensing transistors in a row are connected with each other to form a sensing line 15 across the active regions.
In particular, referring to FIGS. 2 and 3, the selection transistor includes the gate insulation layer 31, the gate electrode, the drain region 35, and the source region. The gate insulation layer 31 is interposed between the word line 13 and the active region. The word line 13 corresponds to the gate electrode of the selection transistor. The drain region 35 is formed by doping first-type impurity ions into one end of the active region. The bit line contact 25 is connected to the drain region 35. The source region serves as the drain region of the sensing transistor.
The sensing transistor includes the gate insulation layer 31 and the tunnel insulation layer 23 formed on a substrate. The tunnel insulation layer 23 is surrounded by a region where the gate insulation layer 31 is formed. The floating gate 19, a dielectric layer pattern 27 and a control gate (a gate electrode of the sensing transistor; 15) are sequentially formed on the gate insulation layer 31 and the tunnel insulation layer 23. The common source line 39 is typically formed by doping first-type impurity ions at a high concentration. The common source line 39 is connected to the sensing transistor through the source region 37. A substrate 10 is doped by second-type impurity ions at a low concentration. Generally, the bit line contact 25 is formed in a contact region and penetrates an interlayer insulation layer 29 to connect a bit line to the active region.
The floating gate 19 is formed wider than the active region enough to stretch over a device isolation layer. Also, the floating gate 19 is isolated from the substrate 10 by the gate insulation layer 31. Likewise, the floating gate 19 is isolated from the control gate 15 by the dielectric layer pattern 27 and sidewall oxide layers 18. Data may be stored in a memory cell by injecting and emitting electric charges in the floating gate 19 through the tunneling insulation layer 23.
For example, while the common source line is grounded or floated and the bit line is grounded, high voltages of 15 to 20V are applied to a word line and the sensing line. Under such conditions, electrons in the substrate are injected into the floating gate through the tunneling insulation layer. That is, the memory cell is under a state of erasion. In this case, a threshold voltage of the sensing transistor is increased up to 3 to 7 V.
By contrast, while the common source line is at a low positive voltage or floated, high voltages are applied to the bit line and the gate line, and a zero voltage is applied to the sensing line. Under such conditions, the electrons in the floating gate are emitted through the tunneling insulation layer. Thus, a threshold voltage of the sensing transistor is decreased to xe2x88x924 to 0V.
To improve erase and program operations of the memory cell, a coupling ratio (CR) must be high. The coupling ratio (CR) is defined as the following equation 1. xe2x80x98Conoxe2x80x99 is a capacitance of a capacitor comprising a control gate, a dielectric layer and a floating gate. xe2x80x98Ctunxe2x80x99 is a capacitance of another capacitor comprising a floating gate, a tunnel insulation layer and a substrate.                     CR        =                  Cono                      Cono            +            Ctun                                              [                  Equation          ⁢                      xe2x80x83                    ⁢          1                ]            
Assuming that the xe2x80x98Ctunxe2x80x99 is a predetermined value, the coupling ratio (CR) is increased with the value xe2x80x98Conoxe2x80x99. Assuming that a dielectric ratio of the dielectric layer is a predetermined value, the capacitance is proportional to areas of opposite electrodes and inversely proportional to a thickness of the dielectric layer. Accordingly, where other conditions are the same, the area of the floating gate should be increased and the thickness of the dieletric layer should be decreased in order to improve the erase and program operations of the memory cell. However, as integration level of memory devices gradually increases, horizontal dimensions of the EEPROM memory cell should be reduced. Accordingly, it is difficult to widely form the floating gate on the substrate. Also, the dielectric layer must have a thickness sufficient to maintain an insulating reliability. Therefore, a thickness of the dielectric layer cannot be continuously decreased.
Meanwhile, due to a breakdown voltage limit, an electric field of the insulation layer cannot be continuously increased with an increase in a voltage applied to the control gate. In addition, the memory device must further comprise a voltage pumping circuit region so as to raise a voltage. And, various portions of a semiconductor device should be formed to endure a high voltage.
It is therefore a feature of the present invention to provide an EEPROM memory cell and a method of forming the same, which can erase and program data with reliability, and also can reduce each area of a cell region and a floating gate to achieve a high integration of a semiconductor device.
It is another feature of the present invention to provide an EEPROM memory cell and a method of forming the same, which can reduce a minimum value of an operating voltage in order to erase and program data with reliability.
The present invention is directed to an EEPROM memory cell that includes a floating gate that is conformally formed in a trench formed at a substrate.
The memory cell comprises a device isolation layer disposed on a predetermined region of the substrate to define an active region in one direction. Source and drain regions are separately formed in a predetermined region of the active region. The trench is formed at the active region between the source and drain regions. A word line crosses the active region between the trench and the drain region. The floating gate is conformally formed on a bottom and sidewalls of the trench. A sensing line crosses the floating gate and is disposed in parallel with the word line. A dielectric layer pattern is interposed between the sensing line and the floating gate, and a tunneling insulation layer pattern is interposed between the floating gate and the active region. A gate insulation layer is interposed between the word line and the active region, and disposed also in the vicinity of the tunneling insulation layer pattern between the word line and the active region. A cell junction region is formed in the active region between the word line and the sensing line.
In accordance with another aspect, the invention is directed to a method of fabricating an EEPROM memory cell that includes a floating gate that is conformally formed in a trench formed at a substrate. The method comprises forming a trench at a predetermined region of the substrate, forming a tunneling insulation layer pattern and a gate insulation layer on an entire surface of the substrate where the trench is formed. The tunneling insulation layer pattern is formed on a trench bottom or on a predetermined region adjacent to the trench. The gate insulation layer is formed on an entire surface of the substrate surrounding the tunneling insulation layer pattern. A first conductive layer is conformally formed on an entire surface of the substrate where the tunneling insulation layer pattern and the gate insulation layer are formed. Thereafter, a dielectric layer is conformally formed on the resultant structure where the first conductive layer is formed. The dielectric layer and the first conductive layer are successively patterned to form a floating gate and a dielectric layer pattern. The floating gate covers a bottom and sidewalls of the trench and the dielectric layer pattern is formed on the floating gate. A second conductive layer is then formed on an entire surface of the resultant structure where the floating gate and the dielectric layer pattern are formed. The second conductive layer is patterned to form a sensing line and a word line. The sensing line crosses the floating gate, while the word line is separated from the sensing line by a predetermined interval and formed in parallel with the sensing line.